Here is the state machine which I'm I'm going to implement using verilog.
This is a very simple state machine which has 4 states. But all the data are is mentioned properly.
*********************Let's look in to the verilog code.**********************************
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module verilogStateMachine(
input in, //single bit input
input clk, //clock
output out //single bit output
);
//registers
reg [1:0]r_state = 2'b00; //state of the state machine, initial state is "00"
reg r_out=0; //register which holds the value of output
always @ (posedge clk) begin
case(r_state)
2'b00 : begin
if (in==0) begin
r_out <=0;
r_state <= 2'b11;
end
else if (in==1)begin
r_out <= 0;
r_state <= 2'b01;
end
end
2'b01 : begin
if (in==0) begin
r_out <=0;
r_state <= 2'b11;
end
else if (in==1)begin
r_out <= 0;
r_state <= 2'b00;
end
end
2'b10 : begin
if (in==0) begin
r_out <=0;
r_state <= 2'b10;
end
else if (in==1)begin
r_out <= 1;
r_state <= 2'b11;
end
end
2'b11 : begin
if (in==0) begin
r_out <=0;
r_state <= 2'b10;
end
else if (in==1)begin
r_out <= 1;
r_state <= 2'b10;
end
end
endcase
end
assign out = r_out; //register value is assigned to output
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
**************************Following is the Test Bench*********************************
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module TB;
// Inputs
reg in;
reg clk;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
verilogStateMachine uut (
.in(in),
.clk(clk),
.out(out)
);
initial begin
clk=0;
in=0;
end
always begin // a virtual clock is generated for simulation purposes
clk = ~clk ;
#5;
end
always begin //Initial state is 00.
in = 1; //state : 00 => 01
#100;
in = 0; //state : 01 => 11
#100;
in = 1; //state : 11 => 10
#100;
in = 0; //state : 10 = > 10
#100;
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
*****************************Timing Diagram using ISim******************************
To get the full view of the Timing diagram, in ISim : View > Zoom > To Full View
